1. Field of the Invention
The present invention relates to computer system, and more particularly to a computer having multi booting function with at least two boot-ROMs having the same address space.
2. Discussion of Related Art
Typically, personal computers have a central processing unit (CPU), storage devices, and input/output devices, as core elements. Also, the storage devices may include a main memory, an auxiliary storage, and a boot-ROM. The boot-ROM stores basic input/output system (BIOS) and a bootstrap loader program executed at the system power-on or reset operation. See, for example U.S. Pat. No. 5,463,766 to Eric Schieve, et al. entitled System And Method For Loading Diagnostics Routines From Disk.
A basic organization of the above mentioned computer system utilizes a CPU connected with the input/output (I/O) devices and storage devices via a system bus. The storage devices may comprise a main memory, an auxiliary storage unit, and a boot-ROM. The CPU controls booting or rebooting of the computer according to a booting program stored in the boot-ROM or ROM-BIOS. Generally, the booting program performs initialization of components of the computer, self diagnostics or a Power-On Self-Test (POST) of the computer system, and reading out an operating system from the boot record of the auxiliary storage unit. Further, the boot-ROM uses an EPROM or an EEPROM device, and recently it tends to use a flash ROM for the convenience of reprogramming intended for functional addition or enhancement.
When the system is powered on and/or reset, the CPU executes booting programs stored in the boot-ROM. Then hardware components initialized and self diagnostics (POST) of the computer system is performed. A determination is then made regarding whether an error has occurred during the self diagnostics. If there is no error, it proceeds to start booting according to the operating system. If an error has occurred, it outputs an error message and ends the booting program.
The computer system having the above-mentioned boot-ROM has shortcomings, however, that the POST diagnostic is limited to the minimum test of the computer hardware due to the limited storage capacity of the ROM device. Thus, the booting program in the boot-ROM is insufficient for full testing of the components of the computer. On the other hand, increasing the capacity of the ROM and performing the full test result in a problem that prolongs booting period.
Further, for supplementing the POST, there may be provided another diagnostic program with the operating system such that it is executed when the booting by the operating system is performed. However, there is a precondition that the POST program is normally performed and the operating system is loaded in the main memory. That is, unstable hardware condition or programming error in the flash ROM prevent the operating system from loading into the computer system, and executing another diagnostic program in the operating system is not possible.
In order to avoid a not being able to use a computer due to a boot failure, U.S. Pat. No. 5,564,054 to Arnold H. Bramnick, et al. entitled Fail-Safe Computer Boot Apparatus And Method contemplates storing at least a minimal number of login files for minimal system configuration in order to boot a computer should an error occur while trying to boot the computer using the login files necessary for full system configuration. U.S. Pat. No. 5,388,267 to Wai-Ming R. Chan, et al. entitled Method And Apparatus For Updating And Restoring System Bios Functions While Maintaining Bios Integrity utilizes redundant boot memories, such as Flash EPROMs, and a user selectable hardware switch so that either boot memory can be selected to boot the computer. U.S. Pat. No. 5,432,927 to Jack A. Grote, et al. entitled Fail-Safe EEPROM Based Rewritable Boot System contemplates the use of a base flash boot memory and an auxiliary flash boot memory wherein both flash memories comprise the same address and necessary boot information, and are selectably enabled in response to a control signal decoded by an address decoder responsive to an address signal output from a central processing unit.